For large-scale deployments, legacy architectures are becoming constrained by two things: memory and communication latency. Processors are getting faster and more powerful, but memory speeds are falling behind; this means the processor spends more and more time waiting for memory. Communications latency is also growing, as data and requests flow in through I/O, are executed by the processor (again waiting for application and data from memory) and then sent back out through relatively high latency I/O. The KNUPATH Hermosa addresses this.
The KNUPATH Hermosa processor uses a super-scalable, performance-advantaged architecture based on neurological design to deliver acceleration of targeted workloads far beyond legacy architectures. We combine distributed computing cores with an ultra-low latency fabric in a massive-bandwidth “push” model, which delivers higher performance from small to ultra-large deployments.
High-speed embedded RAM; 72 MB data in 32 banks. 2 MB program RAM
16 high-speed serial ports at 10 Gbps for a 320 Gbps Bi-directional rate
Built-in instructions for communications, synchronization, aiding scatter/gather capabilities
256 processor cores (tDSPs)
64 programmable DMA engines
Designed to be built into powerful processing arrays allowing up to 512,000 chips addressability.
2^51 longwords (longword = 32 bits) address space
Integrated L1 Router
To cores: 32 ports, 1 Tb/s bandwidth
To other processors: 16 bidirectional 10 Gbps ports = 320 Gbps (multi- dimensional routing)
For more information, please review the Hermosa Series Developer board at http://www.knupath.com/wp-content/uploads/2016/11/KNUPATH-Hermosa-Series-Developer-Board-Product-Brief.pdf.